Verification

You are uncertain about your ASIC, FPGA design, or hardware/software system being implemented as specified, being ready for shipment? You feel the verification effort growing far beyond the design efford itself. That’s our daily business! Today the functional verification of ASICs and FPGAs produces up to 80 percent of the overall design costs. Silicann Technologies will help you to answer the verification engineer’s daily questions:

• Does it work? Is the design behaving as intended?
• Are we done? Has everything being tested?

We have the knowledge to verify your design up to all its limits. Taking the design specification as the base we create a verification plan and run thorough simulations. You benefit from modern methods of functional verification such as

• Hardware/software co-verification
• Object-oriented design of the verification environment with C++/SystemC
• Generation of stimulus with constrained randomization
• Code coverage and functional coverage
• Coverage driven verification.

Based on this methodology we will find design and specification flaws much sooner than with traditional VHDL written direct test cases. For your product this means a shorter time-to-market and reduced costs for after-delivery fixes.

Profit from our verification experiences! Verify your design with us!